[Online] Core-Level Performance Engineering

Monday 5 Oct 2026, 09:00 → 17:00 Europe/Berlin

Online

Core-Level Performance Engineering

Schedule & Format

• Date: 2026, Oct 5
• Time: 9:00 - 17:00 CE(S)T
• Location: Online via Zoom
• Language: English

 

Registered participants will receive the video conferencing link via email on the day before the course.

Further information about the course (content, learning objectives, prerequisites, certification, etc.) can be found on the course page.

Instructor

Dr. Georg Hager, NHR@FAU and Jan Laukemann, NHR@FAU.

This course is organized by Erlangen National High Performance Computing Center (NHR@FAU).

Course Description

Many developers invest heavily in parallelism while overlooking the efficiency of their serial code. Slow serial code tends to scale well in terms of parallel speedup, which can mask the fact that compute resources are being wasted. This course closes that gap by conveying a thorough understanding of the interactions between software and hardware at the level of a single CPU core and the L1 cache. Topics include superscalar out-of-order execution, instruction throughput, critical path and loop-carried dependencies, and the architectural differences between x86 and ARM processors. Participants also learn to read and interpret compiler-generated assembly in AT&T (x86) and AArch64 syntax, and to apply the Open Source Architecture Code Analyzer (OSACA) together with the Compiler Explorer to assess and model performance properties.

Prerequisites

Knowledge

• Programming experience in C or C++ at a level sufficient to read and understand simple loop kernels
• A basic understanding of how CPUs work (registers, instruction execution, data transfers) and what ‘machine instructions’ are.
• A basic understanding of the Roofline model is recommended. You can find some information here (lecture slides) and here (publication by S. Williams).
• Some experience in using the Compiler Explorer is recommended but not required. You can watch a two-part intro by Matt Godbolt: part 1 part 2

Technical

• A modern web browser

Learning Outcomes

After completing this course, you will be able to:

• have a good grasp of the out-of-order processing capabilities of modern server CPUs, specifically x86 and Arm-based server processors such as the Intel Sapphire Rapids and Fujitsu A64FX CPUs,
• understand the concepts of instruction latency, instruction throughput, loop body critical path, and loop-carried dependencies and how they impact loop kernel performance,
• understand how SIMD instructions (i.e., vectorized code) can boost performance and how SIMD and pipelining/out-of-order processing interact,
• be able to work with compiler-generated assembly code,
• be able to employ Godbolt’s Compiler Explorer and the OSACA tool for loop-level in-core performance analysis and modeling,
• understand the impact of in-core execution on the performance of important algorithms from computational science such as sparse solvers, preconditioners, and Lattice QCD,
• understand the limitations of the demonstrated modeling approaches.

Course Structure

• Motivation and basic processor and core architecture of the Intel Sapphire Rapids
• Terminology and code execution on modern out-of-order CPUs
• x86 ISA introduction: understanding scalar and vectorized assembly code
• Performance analysis of simple benchmark kernels
• Introduction to OSACA (Open-Source Architecture Code Analyzer)
• In-core analysis for ARM, including the A64FX core architecture and AArch64 ISA
• Case Study: Sparse Matrix-Vector (SpMV) Multiplication on A64FX
• Case study: Lattice Quantum Chromodynamics (QCD) on A64FX
• Performance analysis, engineering, and optimization for a 2D Gauss-Seidel code on Intel Sapphire Rapids
• Outlook: Static Code Analyzers and the impact of different compilers and compilation flags

Prices and Eligibility

This course is open and free of charge for participants affiliated with academic institutions in European Union (EU) member states and Horizon 2020-associated countries.

Registration

Please register at the bottom of this page. Registration is open until a few days before the course starts, or until the course is fully booked.

Withdrawal Policy

Please only register if you are committed to attending the course. No-shows will be blacklisted and excluded from future events.

If you need to withdraw your registration, please either cancel it directly through the registration system or send an email to nhr-training@fau.de.

Wait List

If the course reaches its maximum capacity, you can request to join the wait list by sending an email to nhr-training@fau.de. Please include your name and university affiliation in the message.

Additional Courses

You can find an up-to-date list of all courses offered by NHR@FAU at https://hpc.fau.de/teaching/tutorials-and-courses/.